A Path Toward Cost-Effective SCA Compliance Testing



Publication Source: Wireless Innovation Forum Conference on Wireless Communication Technologies and Software Defined Radio, SDR-WInnComm, Washington, D.C., USA, 2010

We present R-Check™, a versatile architecture used to develop R-Check SCA, an SCA-specific static-analysisbased compliance testing tool for software radio waveforms. R-Check SCA was developed for JTEL and is intended to provide a cost-effective replacement for several of their search-and-inspect-based compliance testing procedures. The R-Check architecture makes use of several off-the-shelf components and open standards and is specifically engineered to integrate into the widest possible range of vendor development environments, an essential feature for addressing a modest but heterogeneous market space such as software radio.
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Accelerating Regular Expression Processing Using Hardware DFA Engines



Publication Source: The Annual Computer Security Applications Conference (ACSAC), Austin, TX, USA, 2010

The processing of regular expressions (regexes) constitutes a powerful and common detection mechanism in most of network intrusion detection system (IDS). Yet because regular expressions come with significant overheads in terms of both memory and CPU cycles, security network managers have traditionally been conservative in using them.
Article

Automatic Parallelization and Locality Optimization of Beamforming Algorithms



Publication Source: High Performance Embedded Computing Workshop, MIT Lincoln Labs, 2010

This paper demonstrates the benefits of a global optimization strategy using a new automatic parallelization and locality optimization methodology for high performance embedded computing algorithms that occur in adaptive radar systems, for modern multi-core computing chips. As a baseline, the resulting performance was compared against the performance that could be obtained using highly optimized math libraries. Adaptive Beamforming Algorithms Adaptive beamforming algorithms eliminate interference and clutter in a phased array antenna. Typically, for a small number N of array elements, the weight vector application to the incoming sensor stream represents the majority of the computation. However, with the introduction of solid state transceiver elements and the transition to conformal arrays, the number of antenna elements may go into the tens of thousands.
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Generation of High-Performance Protocol-Aware Analyzers with Applications in Intrusion Detection Systems



Publication Source: In Cyber Security, Situation Management, and Impact Assessment II; and Visual Analytics for Homeland Defense and Security II, SPIE Proceedings Vol. 7709, 2010

Traditional Intrusion Detection and Prevention (IDP) systems scan packets quickly by applying simple byte-wise pattern signatures to network flows. Such a protocol-agnostic approach can be compromised with polymorphic attacks: slight modifications of exploits that bypass pattern signatures but still reach corresponding vulnerabilities. To protect against these attacks, a solution is to provision the IDP system with protocol awareness, at the risk of degrading performance. To balance vulnerability coverage against network performance, we introduce a hardware-aware, compiler-based platform that leverages hardware engines to accelerate the core functions of protocol parsing and protocol-aware signature evaluation.
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A Mapping Path for Multi-GPGPU Accelerated Computers from a Portable High Level Programming Abstraction



Publication Source: 3rd Workshop on General Purpose Processing on Graphics Processing Units (GPGPU), Pittsburgh, PA, USA, 2010

Programmers for GPGPU face rapidly changing substrate of programming abstractions, execution models, and hardware implementations. It has been established, through numerous demonstrations for particular conjunctions of application kernel, programming languages, and GPU hardware instance, that it is possible to achieve significant improvements in the price/performance and energy/performance over general purpose processors. But these demonstrations are each the result of significant dedicated programmer labor, which is likely to be duplicated for each new GPU hardware architecture to achieve performance portability.
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