R-Stream: A Parametric High Level Compiler

Publication Source: High Performance Embedded Computing Workshop (HPEC), Lexington, MA, USA, 2006

This presentation describes the R-Stream compiler. The motivation of high level, source to source optimization is described. The process or raising code to the Generalized Dependence Graph (GDG) is identified, and then the techniques for optimization within the GDG.  Finally, the techniques for code generation from the GDG - polyhedral scanning, and importantly, the process of generating "human readable" C to allow the low level compiler to optimize.
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Enabling Cognitive Architectures for UAV Mission Planning

Publication Source: The High Performance Embedded Computing Workshop (HPEC), Lexington, MA, USA, (Best papers award session), September, 2006

The operational performance desired for autonomous vehicles in the battlefield requires new approaches in algorithm design and computation. Our design, Polymorphic Cognitive Agent Architecture (PCAA), is a hardware-software system that supports the requirements for implementing a dynamic multi-unmanned aerial vehicle (UAV) mission planning application using cognitive architectures. We describe the requirements for our application, and discuss the challenges of using current “non-cognitive” algorithms to solve this problem and the reasons this motivates our experiment.
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Runtime Verification of Cognitive Applications

Publication Source: The 10th Annual High Performance Embedded Computing Workshop (HPEC), Lexington, MA, USA

Cognitive systems have been the subject of much research, and are increasingly of interest in embedded systems. However, cognitive applications have unique characteristics that make them challenging to verify, validate, and debug. A cognitive application by definition makes intelligent decisions – if it were possible to formally and precisely express its behavior under all circumstances, the cognitive system would not need to be “cognitive.”
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Salt & Alef: Unlocking the Power of Boolean Satisfiability

Publication Source: The 10th Annual High Performance Embedded Computing Workshop (HPEC), Lexington, MA, USA, 2006

Solvers for the Boolean satisfiability problem (SAT) are an enabling technology for a diverse set of applications relevant to the HPEC community. These applications include formal verification, analysis of numerical precision for embedded pipelines, and cognitive reasoning. However, solver performance, measured in terms of speed and maximum problem size, is a limiting factor to the application of SAT to real-world problems. We are developing a constraint language, translation tool, and parallel SAT solver to significantly mitigate the impact of these limitations.
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Alef Verification and Planning System

Publication Source: The 48th Annual Cray User Group (CUG) Technical Conference, Lugano, Switzerland, 2006

Recently, solvers for the Satisfiability problem (SAT) have become an enabling technology for diverse areas of military and commercial interest. However, solver performance, in terms of speed, maximum problem size, and efficiency, is a limiting factor to the more extensive application of this technology. This paper discusses Reservoir's SAT-based planning and verification system, Alef, which includes a compiler, intermediate language, and parallel solver for HPC hardware. 
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