R-Stream 3.0: Technologies for High Level Embedded Application Mapping
09/01/2004Publication Source: The 8th Annual High Performance Embedded Computing (HPEC) Workshops, Lexington, MA, USA, 2004
R-Stream is a High Level Compiler being developed as part of the DARPA IPTO Polymorphous Computer Architecture Program. The compiler is targeted at the problem of mapping high performance embedded signal/knowledge processing applications. Our 2.0 version, presented as a poster at HPEC last year, will be performing application mapping via the Streaming Virtual Machine interface to low level compilers (LLC). This presentation will focus on the implementation and architecture of the high level compiler (HLC). In particular, we will present the performance results and insights from our 2.0 version of our Integrated Radar Tracker (IRT) running simulated on the reference Polymorphous Computer Architecture (PCA). The performance results will be accompanied by details of the application transformations that 2.0 will be performing, including granularity selection, high level streaming transformations, and the manner in which we integrate the data parallel front end of IRT with the more task/thread parallel back end. Furthermore, we expect to be able to provide insight into the benefits and limitations of some aspects of the morphware software architecture, in particular the phased HLC/LLC compilation structure, the SVM interface, and the abstraction of architectures into the Streaming Machine Model (SMM) and Hierarchical Machine Model (HMM). We may further be able to accompany this with some performance results for the application mapped to commercial architectures that are emerging with similarities to the PCA architecture class.
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