Compiler R&D

Enabling advanced computing hardware.



Explore our LLVM expertise

Reservoir Labs has a team experienced with LLVM development and can provide services to help you apply LLVM to your application or target architecture.

Reservoir Labs offers technology enabled services helping our customers apply LLVM to their systems and architectures. Our team is qualified and experienced in compiler development, with experience on many different compiler platforms and many different architectures, bringing this to LLVM projects. We have team members qualified to work on the entire tool chain from front end to code generation. We are delivering services that range from new language feature support, through new optimizations, to new code generation capabilities for novel instruction set architectures. Reservoir’s general expertise in high-performance computing, including advanced algorithms, helps us to understand the specific requirements of customers.


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Core Capabilities

Instruction Scheduling

We have experience related to instruction scheduling, including DAG scheduling and modulo scheduling modules. We have done careful work on instruction scheduling in the context of predication and the use of looping instructions.

LLVM tools

We have delivered LLVM-as and linker. We have also ported LLDB to new architectures. We have experience with the interaction between TableGen and these components.

Loop optimization

We have experience with LLVM’s basic loop optimization passes. For advanced loop optimization, we offer R-Stream, a polyhedral optimizer that plugs into LLVM.

Code Generator

Our team has expertise developing support for new instruction sets, including instruction sets with novel instructions, predication, and vector extensions. Novel instructions can be generated various ways – via instruction selection, intrinsics, builtins, and inline assembly. We have improved TableGen including for debuggability of code generation. Our team has also written and delivered new back ends for processors with novel ISAs related to domain-specific optimizations.


We have experience with vector instruction, vector register, and vector memory assignments.

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